参考：questions on M5 stats、difference between demand and overall accesses
当用gem5中classic memory mode运行测试集后，查看stats.txt，可看到如下结果：
system.l2.ReadExReq_accesses::total 12365514 # number of ReadExReq accesses(hits+misses)
system.l2.ReadReq_accesses::total 73364986 # number of ReadReq accesses(hits+misses)
system.l2.demand_accesses::total 85730500 # number of demand (read+write) accesses
system.l2.overall_accesses::total 85730500 # number of overall (read+write) accesses
system.l2.Writeback_accesses::writebacks 67311441 # number of Writeback accesses(hits+misses)
system.l2.Writeback_hits::total 67311441 # number of Writeback hits从上述结果看出，demand_accesses (overall_accesses) = ReadExReq_accesses + ReadReq_accesses, overall_accesses == demand_accesses。
那么问题来了，write accesses哪里去了？
为了理解这些统计数据间的关系，需要查看src/mem/cache/base.cc文件关于统计数据间关系的定义，实际上：
demand_accesses = ReadExReq_accesses + ReadReq_accesses + WriteReq_acesses, overall_accesses = demand_accesses + non-demand_accesses (实际上是硬件预取和软件预取)。
那么WriteReq_acesses和non-demand_accesses去哪儿了？
non-demand_accesses是由于默认情况下预期机制没有开通，需要自己修改；
WriteReq_acesses是由于classic memory默认的缓存策略是writeback和write allocation，所以没有WriteReq_acesses，全是writeback。同时发现上面的数据中Writeback hits 和total结果一样，意思是说没有miss，实际上它是根据write allocation策略，写回没命中时，则从主存中去取数据再写，并认为一直是命中。