Verilog array for synthsis

integer i,j;
always @(posedge i_clk or negedge i_rst_n)begin
if(!i_rst_n)begin
for(i = 0; i < i_wghtGridH; i = i + 1)begin
for(j = 0; j < i_wghtGridW; j = j + 1)begin
r_WeightoNWeights0a[i][j] <= 5‘d0;
end
end
end
else begin
r_WeightoNWeights0a[texel_cnt_y_r2][texel_cnt_x_r2] <= w_WeightoNWeights0;
end
end
why design compiler 2010 think this is not right?
Because i_wghtGridH is a variable.

This is ok.
reg [4:0] r_WeightoNWeights0a [7:0][7:0];
integer i,j;
always @(posedge i_clk or negedge i_rst_n)begin
if(!i_rst_n)begin
for(i = 0; i < 8; i = i + 1)begin //num_plp can use wire ??
for(j = 0; j < 8; j = j + 1)begin
r_WeightoNWeights0a[i][j] <= 5‘d0;
end
end
end
else begin
r_WeightoNWeights0a[texel_cnt_y_r2][texel_cnt_x_r2] <= w_WeightoNWeights0;
end
end

1.因此array的索引号必须为常数。若texel_cnt_y_r2不为常数，也不合理。

2.Verilog Array 在verdi中看不到波形，所以array建议写成switch-case的方式来选择索引号。